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Freescale Semiconductor /MK70F15WS /PIT /TCTRL1

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Interpret as TCTRL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)TEN 0 (0)TIE 0RESERVED

TEN=0, TIE=0

Description

Timer Control Register

Fields

TEN

Timer Enable Bit.

0 (0): Timer n is disabled.

1 (1): Timer n is active.
TIE

Timer Interrupt Enable Bit.

0 (0): Interrupt requests from Timer n are disabled.

1 (1): Interrupt will be requested whenever TIF is set.
RESERVED

no description available

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data